1. Field of the Invention
The present invention relates to an electric circuit substrate having an electrode part to which integrated circuit devices (IC) or semiconductor bare chips are connected.
This application claims priority of Japanese Patent Application No. 2003-299266, filed on Aug. 22, 2003, the entirety of which is incorporated by reference herein.
2. Description of the Related Art
In recent years, in order to achieve the miniaturization of a liquid crystal display device, integrated circuit devices (IC) or semiconductor bare chips serving as a driving circuit, a peripheral circuit or the like are directly attached to a peripheral edge part of a glass substrate on which a liquid crystal display part is formed.
For instance, when an IC 101 is directly attached to a peripheral edge part of a glass substrate 202 around a liquid crystal display part 201, as shown in FIG. 1A, protrusion shaped bumps 102 serving as connecting terminals are provided on a bottom surface part 103 of the IC 101. Further, as shown in FIG. 1B, on the peripheral edge part of the glass substrate 202 around the liquid crystal display part 201, electrode parts 203 exposed upward are formed. Further, as shown in FIG. 1C, while the bumps 102 are arranged at positions corresponding to the electrode parts 203, the IC 101 is attached under pressure to the liquid crystal display part 201 through an anisotropic conductive film 301 from an upper part toward a lower part. Thus, the IC 101 is fixed to the peripheral edge part around the liquid crystal display part 201 and the inner wirings of the IC 101 is connected to the inner wiring of the liquid crystal display part 201.
Now, a process for forming the electrode parts 203 formed on the peripheral edge part around the liquid crystal display part will be described in more detail.
As shown in FIG. 2A, on the glass substrate 202 on which the liquid crystal display part is formed, interlayer dielectric films 204 are formed. Further, between the glass substrate 202 and the interlayer dielectric films 204, metal wiring 205 is formed. When the electrode parts 203 are formed, the interlayer dielectric films 204 are firstly partly opened to form opening parts 206 and the metal wiring 205 is exposed upward from the opening parts 206. Then, as shown in FIG. 2B, on the opening parts 206, electrode pads 207 made of a metallic material are formed. At this time, the electrode pads 207 are formed in areas larger than the opening parts 206 so as to assuredly come into contact with the metal wiring 205. That is, the electrode pads 207 are formed at positions including the interlayer dielectric films 204 around the peripheral edge parts of the opening parts 206.
Subsequently, as shown in FIG. 2C, planarizing films 208 having an insulating property are formed, and then, parts on which the electrode pads 207 are formed are opened to complete the electrode parts 203.
In the usual electrode parts 203 as described above, between the peripheral edge part of the electrode pad 207 and the central part of the electrode pad 207, a step (difference in position in the direction of the thickness of the film, for instance, a part A1 in FIG. 3) is generated. On the interlayer dielectric film 204, a step corresponding to the thickness of the electrode pad 207 (for instance, a part A2 in FIG. 3) is generated. Ordinarily, for the purpose of eliminating the steps, the planarizing films 208 having the insulating property are used for coating. However, a complete planarization is difficult (for instance, a part A3 in FIG. 3).
While the planarization process is not completely performed, when the bumps 102 of the IC 101 are attached under pressure and connected to the electrode pads 207, a displacement is generated in the direction of thickness of the film in the connecting parts of the electrodes pads 207 and the bumps 102 (for instance, a part A4 in FIG. 3) to cause a defective electric connection.
In the usual electrode parts 203, the electrode pads 207 are formed to protrude onto the interlayer dielectric films 204. Thus, the electrode pads 207 of the adjacent electrode parts 203 may come into contact with each other (for instance, a part A5 in FIG. 3). Further, such a failure as to break the interlayer dielectric films 204 or the electrode pads 207 may be generated due to a slight displacement in a planar direction, which constitutes a factor of causing the yield or reliability of a product to be lowered. Further, the electrode pads 207 are formed to protrude onto the interlayer dielectric films 204, so that pitches between the adjacent electrode parts 203 are restricted and the pitch are hardly narrowed.
Further, in recent years, to reduce wiring resistance, the thickness of a wiring pattern and the thickness of the electrode pads are increased. Accordingly, on the interlayer dielectric film 204, the step corresponding to the thickness of the electrode pad 207 is formed. This step is undesirably more increased. As a result, a step in an irregular part on the planarizing film 208 is increased (for instance, a part A3 in FIG. 3). Accordingly, a deficiency that the pattern of the planarizing films 208 is stripped is undesirably generated (see Japanese Patent Application Laid-Open No. hei 10-161140).